This is invention relates generally to static random access memory (SRAM) cells and particularly to semiconductor on insulator (SOI SRAM cells which utilize polysilicon resistors formed in trenches.
Presently, using complementary metal oxide silicon (CMOS) technology, SRAM cells are constructed using either a four transistor or a six transistor implementation. Typically, the four transistor configuration uses a polysilicon load element which functions as a passive resistor. The load resistors are generally situated horizontally over the active cell elements to reduce the cell area. See, for example, T. Ohzone, T. Hirao, K. Tsuji, S. Horiuchi, and S. Takayanagi, A 2Kx8-Bit Static MOS RAM with a New Memory Cell Structure, IEEE J. Solid-State Circuits, vol. SC-15, pp. 201-205, April. 1980.
The four transistor configuration has the advantage of a small size. The four transistor configuration has the disadvantage of requiring a more complex process than a six transistor implementation. The four transistor configuration also has the disadvantage of a higher standby current.
The six transistor configuration has the advantage that it can easily be implemented in the standard ASIC CMOS process. However, SRAM cells which utilize the six transistor configuration are larger than SRAM cells which utilize the four transistor configuration and are more susceptible to latch up. Latch up occurs when the four-layer NPNP CMOS structure acts like a silicon controlled rectifier (SCR) and switches from a high impedance state to a low impedance state in response to a triggering signal. This latch up is detrimental and sometimes destructive to the integrated circuit.